Module floorplan 

Floorplans read off a fitted build: a Logic Lock region for each instance named, a square beside the site its clock comes from, as small as what the instance needs at the parent region’s density allows, inside the parent region.

The build says everything the floorplan needs. Its clock table names each clock’s target cell, and the fitter’s fast-signal table the site of each net it put on a fast network: a clock’s site is the fast signal sharing its target’s deepest hierarchy (an EMIF’s user clock leaves its IO tile’s control, the net beside it). An instance’s clock is the one its timing paths run on, both ends inside it. Its need is the fitter’s own entity table (ALMs needed, M20Ks), and the parent region’s density its capacity over its sites. The region is then the square that holds the need at a fill (half by default, room for the router), every site of it in the parent region, the nearest such square to the clock’s site. Quartus takes it as a PLACE_REGION with CORE_ONLY_PLACE_REGION on and RESERVE_PLACE_REGION off, so the rest of the design may share the sites.

Structs

Anchor

Where an instance’s clock comes from: the instance, the clock its paths run on, and the site that clock leaves (a memory channel’s, its bank’s IO tile control).

Anchors

The anchors ledger (benchmarks/silicon/d5005/emif_anchors.json): what it holds, the build whose reports placed the anchors, the day they were recorded, and the anchors.

Assignment

One region: the instances it holds, the name Quartus gives it, its rectangle.

Capacity

What a tile holds, as the fitter counted it.

Density

A region’s resources a site: its ALMs and its M20Ks over its sites.

Fill

How much of a region a unit may take of each resource: of its logic (ALMs and registers), the rest room for the router and for the logic that shares the region; of its M20Ks and its DSP blocks, hard blocks that need no such room.

Geometry

The device’s capacity map, as a probe’s fit counted it: each tile and what it holds.

Need

What an instance needs of a region: its ALMs needed and its M20Ks.

Needs

What a unit needs placed.

Ram

A memory as synthesis left it: its path, the block it asked for (AUTO, M20K block, MLAB), each port’s depth and width, its byte enables’ byte when it has them, and whether a read on one port during a write on the other must give the old data.

Rect

A rectangle of sites, both corners inclusive.

Region

A unit’s region of whole tiles: the instance, its name, its tiles in the map’s order (top row first, then left).

Unit

A unit the floorplan places: the instances its one region holds, the region’s name, what they need together.

Enums

AnchorError

Why a build’s reports place no anchor for an instance.

PlaceError

Why a floorplan places no region.

Wire

A bus the floorplan keeps short, weighted by its width in bits: between two units, by their index, or between a unit and a fixed site.

Functions

anchor

The anchor of instance from a fitted build’s reports: the clock its setup paths run on (instance_clock), that clock’s targets in the clock table, and the fast signal of the place report those targets come from (clock_site).

candidates

Every rectangle of whole tiles of geometry that holds needs at fill, overlaps none of blocked, is no longer than aspect times its width in sites, and is least: no rectangle a tile row or column smaller inside it holds the needs too. In order of their top row, then left column, then size.

clock_site

The site a clock comes from: the fast signal sharing one of its targets’ deepest hierarchy, or none when no fast signal shares any level or two share the deepest.

clock_targets

Every clock of the timing analyzer’s Clocks table with its target cells.

device

The device’s sites: the route region of the fit report’s Logic Lock Region Constraints, the whole core a flat build may place in. It is a row’s last cell: the place region before it separates its rectangles with the table’s own ;.

fabricless

The tiles a probe’s fit found no flip-flop in: each region its log refuses as needing a flip-flop where there are none (Deterministic overuse of FF resources in region (x0,y0) to (x1,y1)), a tile of the device with no logic (hard IP, the core’s edge), which the next probe leaves out and no floorplan places a region on.

fast_signal_sites

Every net of the fit report’s Global & Other Fast Signals Summary with the site it is driven from.

grow

The floorplan of units in regions of whole tiles, each unit in the order given. Its seed is the free tile where its wires are shortest (each wire’s width times the straight distance from the tile’s centre to the centre of the unit at its other end, placed before it, or to its fixed site), among the free tiles of an area that holds it at fill, the top row and left column first on a tie. The region then takes, one at a time, the free tile beside it nearest the centre of its sites so far (then where the wires are shortest, then the top row and left column) until it holds the unit, so it grows as compact as the tiles allow and bends round what is taken. A tile is free when no region before it took it and it overlaps nothing blocked. A unit no free area holds is refused by name.

holds

Whether a region of capacity holds a unit of needs at fill: each resource the unit needs within its share of the region’s.

instance_clock

The clock an instance runs on: the latch clock of the most setup paths in the timing report whose both ends lie inside it, none when no path does or two clocks tie.

instance_need

An instance’s need as the fit report’s Fitter Resource Utilization by Entity states it (its totals, itself and everything under it).

loose

The instances of graph no unit of units holds, each with the bits its links carry to the units’ instances, heaviest first (then by path), those carrying none left out: a path between two units through an instance no unit holds is no wire of the floorplan’s (unit_wires counts links between units’ instances alone) until its module is dissolved into the graph (netlist::module_graph’s through).

m20k_blocks

The M20K blocks a memory of depth words of width bits takes: the fewest over the block’s simple-dual-port shapes (512 × 40, 1,024 × 20, 2,048 × 10), as many blocks side by side as its width needs and stacked as its depth does, the stack a power of two deep (the fitter decodes it by the address’s top bits).

parent_region

The parent region a build’s floorplan lies in: the rectangles of its one Logic Lock region (a partial reconfiguration build’s persona), with that region’s density.

place

The floorplan of units, each in the order given at its candidate of least cost: the width of each of its wires to a unit placed before it or to a fixed site, times the straight distance between centres, so a unit sits where its wires meet; a candidate overlaps no unit placed before it nor blocked. Ties go to the smaller perimeter (the more compact region), then area, then the top row and left column. A unit no candidate holds is refused by name.

probe

The geometry probe for tiles: a design of one register cell a tile (c<k>), and the Logic Lock region pinning each cell to its tile (geo_<k>), so a fit of it reports every tile’s capacity in its region usage.

region

The square that holds need at fill of density, every site of it in parent, nearest anchor: the least side whose sites hold the need, then of its placements the one nearest the anchor (Chebyshev), then the one whose centre is nearest, then the lowest. None when no placement of that side fits, or the density holds none of what is needed.

region_name

A Logic Lock region’s name for an instance path: logos_ and the path, its levels and a generate block’s scope parted by _, an index’s brackets dropped (ch[0].channel is logos_ch0_channel).

regions_tcl

The regions as Quartus settings: each a PLACE_REGION of its rectangles (Region::rects), its own name, core sites only, shared with the rest of the design.

site

The site of a location the fitter names, TILECTRL_X233_Y36_N2 its (233, 36).

synthesized_needs

What the instances members need placed together as Quartus synthesized them, from the synthesis report syn: the entity table’s ALUTs, registers and DSP blocks of each member’s whole subtree summed, those ALUTs and registers in ALMs at packing packed as one (the fitter packs one member’s registers beside another’s LUTs), and the M20K blocks the fitter gives every memory under any of them (Ram::m20k). The member the entity table does not name, when one is missing.

synthesized_rams

Every memory of the synthesis report’s RAM summaries (one a partition), each with what its inferred parameter section (Parameter Settings for Inferred Entity Instance: <path>, the path its name continues) says of its byte enables and of a read across its ports; a memory no section names has neither.

tcl

The assignments as Quartus settings: each region a PLACE_REGION of every instance it holds, under its one name, core sites only, shared with the rest of the design.

tiles

The device cut into tiles of width columns by height rows from its corner, row by row, the last of each row and column clipped to the device.

unit_floorplan

The floorplan of units in rectangles (place) on the wires unit_wires reads off the module’s graph.

unit_regions

The floorplan of units in regions of whole tiles (grow) on the wires unit_wires reads off the module’s graph.

unit_wires

The units a floorplan places and its wires, from a module’s graph: each of units (its instances paths under the module graph was read from, its region’s name, what its instances need together) placed under under (the module’s own path in the build); a wire between two units of the bits the graph counts between an instance of the one and an instance of the other (bits between two instances of one unit stay inside its region); and from a unit to an anchor (matched by an instance’s full path) of the bits that instance shares with the module’s ports, the way out to the anchor. Refused by name: an instance the module lacks, a unit of none, an instance two units hold, and two units of one region name.