pub fn emit_state_soc() -> StringExpand description
The SIMPLE state SoC (state_soc) for the iverilog proof: it wraps state_<name> with a CYCLE COUNTER
(cycles from reset-release to done) and exposes result/cycles/done. A host/testbench presents
(a,b,c), pulses rst, and reads back the multi-cycle result — the board-independent ≡VM proof surface.