Module fabric_soc 

fabric_soc — Phase E: the FLASHABLE reconfigurable-fabric SoC.

Phase D proved (our SAT) that a diverse program corpus projects onto ONE reconfigurable tile array under a config word. This module makes that array real hardware: a synthesizable fabric_soc wraps the config_<name> array (emit_config_grid_verilog) with registered I/O and a CYCLE COUNTER, so a host presents (cfg, inputs) and reads back (result, cycles). Because the array is feed-forward (combinational), a decision settles in ONE clock — the honest cycles/op the interpreter pays hundreds of fetch-decode-execute cycles for. The self-checking testbench drives the SoC over a vector battery and $displays (result, cycles); fabric_soc_lock runs it under iverilog and checks every result against the VM and every cycle count against the 1-clock settle. The RTL, its testbench, and the constraints are drift-locked (regenerate with FABRIC_SOC_RECORD=1), and the config-grid ≡ VM is the eval side of fabric_whole_program_lock (Phase D).

Constants

CFG_WIDTH

FABRIC_SOURCES

The fabric SoC’s program corpus — the datapaths the ONE reconfigurable array can become, selected by the config word. Single-final-Return + conditional-Set style so branches if-convert to select tiles.

FLOAT_SOC_NAME

FLOAT_SOC_SRC

The flashed float kernel: fhypf(a,b) = sqrt(a*a + b*b) — the Euclidean hypotenuse as a Real. Exercises the full float lane: fp_mul (twice) + fp_addsub + fp_sqrt. It returns a FLOAT (not floored) so the SoC streams the raw f64 bits — the host floors to the integer hypotenuse (no float→int RTL needed on-chip).

N_IN

The SoC’s input-port count — the max arity over the corpus (clamp has three). Functions with fewer inputs ignore the extra ports (their tiles never reference them).

STATE_SOC_NAME

STATE_SOC_SRC

The flashed state-plane kernel: grade(a,b,c) is a WHOLE MULTI-OP-CLASS program — it builds the list [a,b,c] on the heap (COLLECTIONS), sums its elements (ARITHMETIC), and clamps the total to [0, 100] (CONTROL FLOW — two if-converted branches). So the flashed datapath exercises three distinct op-classes at once — Mem (HeapAlloc/Write/Read) + Arith (adds) + Select (the clamps) — all in ONE sequenced datapath on silicon: the fabric running a real program, not a single op.

WIDTH

The datapath / config-word widths (8-bit datapath for the SAT proof; 3-bit config indexes ≤ 8 datapaths).

Functions

emit_config_grid

The reconfigurable array RTL (config_fabric): ONE tile grid becoming any corpus datapath under cfg.

emit_fabric_soc

The flashable SoC: registered (cfg, inputs) in, the combinational config_fabric, a cycles counter, and registered (result, cycles, done) out. On rst release the array’s output settles in one clock; the SoC latches it, sets cycles = 1 (the honest cost of a spatial decision), and raises done. Synthesizable as-is — the inputs wire to switches / a UART loader and the outputs to LEDs / a UART readback for bring-up.

emit_fabric_soc_tb

The self-checking testbench: drive the SoC over (cfg, inputs) vectors and $display cfg result cycles per vector. fabric_soc_lock parses these and checks each result ≡ the VM and each cycle count == 1.

emit_float_soc

The SIMPLE float SoC (float_soc) for the iverilog proof: float_<name> under a CYCLE COUNTER, exposing the f64 result bits / cycles / done. A testbench presents float bit-patterns and reads the result.

emit_float_soc_module

The sequenced float datapath RTL (float_fhypf) — the fpu.v-bound micro-sequencer for the kernel.

emit_float_soc_tb

A self-checking testbench for float_soc: drive each float pair (bit-patterns), run to done, and $display(\"result_hex cycles\"). float_soc_lock runs it under iverilog (with fpu.v) and checks each result’s f64 bits ≡ the model/Rust and each cycle count > 1.

emit_nexys_fabric_soc

Emit the BOARD-FLASHABLE top (nexys_fabric_soc) for the Nexys A7-100T: the reconfigurable config_fabric array, a baked-in vector ROM, and a settle sweep that measures on the chip how many clocks each datapath takes. For every vector the sweep loads a prime into the launch register, lets it settle, launches the vector and captures the array’s output L clocks later, for L from LMAX - 1 down to 1, under two primes (the vector’s inputs inverted, and the next vector), REPS times. The settled value is the capture at 2·LMAX; a result is settled inside the window only when the capture at LMAX already equals it under both primes. The streamed cycle count is the smallest L from which every capture equals the settled value, the worst over the repetitions, and 0 when the result did not settle inside the window. Each record goes out the UART TX as (sync, cfg, result[8], cycles[2]); a host checks each result against the VM. 100 MHz board clock, 115200 baud (CLKS_PER_BIT = 868). Pins in nexys_fabric_soc.xdc.

emit_nexys_fabric_xdc

The board pin constraints for nexys_fabric_soc (Nexys A7-100T): 100 MHz clock (E3), reset (J15), UART TX (D4), status LEDs. No uart_rx — the vector ROM is baked in, so the SoC only streams out.

emit_nexys_float_soc

The FLASHABLE float SoC (nexys_float_soc) for the Nexys A7-100T: a baked-in (a,b) float ROM drives float_<name> — pulse the datapath reset, wait done (counting the FPU pipeline cycles), capture the f64 result, and stream the 12-byte record {0xA5, vec, result[63:0] MSB-first, cycles[15:0]} out the UART TX, looping forever. The host decodes the f64 and floors it to the integer hypotenuse. 100 MHz; 8N1 115200.

emit_nexys_float_xdc

The Nexys A7-100T pin constraints for nexys_float_soc — same ports as the fabric SoC, same pin map.

emit_nexys_state_soc

The FLASHABLE state SoC (nexys_state_soc) for the Nexys A7-100T: a baked-in (a,b,c) vector ROM drives state_<name> — pulse the datapath reset, wait done (counting the multi-cycle latency), capture the result, and stream the 12-byte record {0xA5, vec, result[63:0] MSB-first, cycles[15:0]} out the UART TX, looping forever so a host can frame-lock at any time. 100 MHz; 8N1 115200 (CLKS_PER_BIT=868).

emit_nexys_state_xdc

The Nexys A7-100T pin constraints for nexys_state_soc — identical ports to the fabric SoC (100 MHz clk, reset, UART TX, LEDs), so the same pin map.

emit_state_soc

The SIMPLE state SoC (state_soc) for the iverilog proof: it wraps state_<name> with a CYCLE COUNTER (cycles from reset-release to done) and exposes result/cycles/done. A host/testbench presents (a,b,c), pulses rst, and reads back the multi-cycle result — the board-independent ≡VM proof surface.

emit_state_soc_module

The sequenced state-plane datapath RTL (state_grade) — the LUTRAM-heap micro-sequencer for the kernel.

emit_state_soc_tb

A self-checking testbench for state_soc: drive each (a,b,c) vector, pulse rst, run until done, and $display(\"result cycles\"). state_soc_lock runs it under iverilog and checks each result ≡ the VM and each cycle count > 1 (a sequenced state program, not a 1-clock combinational decision).

fabric_grids_json

The placed-and-routed tile arrays as JSON — the source of truth for every technical drawing of the fabric, so a drawing of a tile array is the placer’s own output, never hand-drawn. Contains the five config_fabric islands (the 8×3 array that runs 14/14 vectors on both boards) and the Horner cubic residual on both placers (the diagonal route_straight_line behind grid_horner.v, and the area-minimizing route_leveled). Pinned to benchmarks/silicon/fabric_grids.json by fabric_grids_lock.

float_soc_vectors

The (a, b) float pairs the float SoC runs on silicon → each hypotenuse (mostly Pythagorean integers).

state_soc_vectors

The input battery the state SoC runs on silicon (each a (a,b,c) triple → clamp(a+b+c, 0, 100)). Chosen to exercise the pass-through, the UPPER clamp (sum > 100), and the LOWER clamp (sum < 0) — so the control flow is genuinely taken on hardware, not just present.

table

The compiled config table (padded islands on one array). The single source of truth for the RTL and the testbench’s expected values — both derive from it, never hand-typed.

vectors

The test vectors the testbench drives — a battery per datapath, spanning each function’s cases. Kept in sync with fabric_soc_lock’s expected computation (both iterate this same list).