pub fn emit_while_fabric_verilog(name: &str, wf: &WhileFabric) -> StringExpand description
Emit the while-CGRA as a SEQUENTIAL circuit: a combinational body datapath + a controller whose
running flag is the FABRIC PREDICATE — evaluated on the init state (at reset) and on the next
state (each step) to decide whether to keep iterating. No counter: the trip count is data.