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emit_state_plane_verilog

logicaffeine_compile::codegen_sva::fabric_rtl

Function emit_state_plane_verilog 

Source 
pub fn emit_state_plane_verilog(
    name: &str,
    df: &DecisionFabric,
    heap_words: usize,
) -> String
Expand description

Lower a heap-bearing DecisionFabric to a SEQUENCED state-plane controller (see the block comment above). heap_words sizes the shared LUTRAM. Pure-compute cells render as combinational v{i} wires (over the LATCHED cell registers R[j]) latched per step; heap cells access the LUTRAM with a bump-pointer hp.