Function emit_seqprog_soc_verilog 

pub fn emit_seqprog_soc_verilog(
    name: &str,
    pf: &ProgramCfgFabric,
    vectors: &[Vec<i64>],
) -> String

Emit a Nexys A7 SoC wrapper for the whole-program sequenced fabric: a baked vector ROM steps seqprog_{name} through each input (drive params → pulse the fabric reset → wait done → capture result), streaming a 12-byte record {0xA5, result[63:0] MSB-first, run_cycles[15:0], 0x5A} out the UART TX per vector, then looping. Slow /128 core clock (781.25 kHz) + power-on reset. vectors are the params per run (n_params each). This is the multi-cycle fabric (division + fpu.v tiles) on real silicon.