Function emit_seq_block_verilog 

pub fn emit_seq_block_verilog(name: &str, block: &CfgBlock) -> String

Emit a per-block SEQUENCED datapath (seqblk_{name}) for a CfgBlock: on a start pulse it walks the block’s SSA cells (combinational in one step, multi-cycle division/float via the shared units), then holds done high with every needed output (each register write’s Src, then the terminator operand) driven from the settled cell/register values. The block-walk sequencer starts it, waits done, latches the writes, and evaluates the terminator. Multi-cycle TILES are first-class here.