pub fn emit_pow_datapath_verilog(name: &str, df: &DecisionFabric) -> StringExpand description
Lower a pure-Pow DecisionFabric to a SEQUENCED power datapath (see the block comment above). Each cell
is one b-step multiply loop over a shared accumulator; the streamed result is the final power. Panics
on any non-Pow cell (the honest boundary — mixed lanes are a follow-on).