Function emit_nested_fabric_verilog 

pub fn emit_nested_fabric_verilog(name: &str, nf: &NestedFabric) -> String

Emit the nested CGRA as a HIERARCHICAL FSM: an outer counter that, per iteration, sets up the inner range (from the outer iv) and runs the inner counter to completion, streaming the shared state through the inner body datapath. Three states — SETUP (arm inner for oi), RUN (inner iterates), and advance-outer — so the inner range recomputes correctly when the outer advances.