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emit_loop_fabric_verilog_int8

logicaffeine_compile::codegen_sva::fabric_rtl

Function emit_loop_fabric_verilog_int8 

Source 
pub fn emit_loop_fabric_verilog_int8(
    name: &str,
    lf: &LoopFabric,
    mul_bits: u32,
) -> String
Expand description

Emit the CGRA RTL with an INT8-NATIVE datapath: every multiply tile’s operands are mul_bits-bit signed, so each MAC maps to exactly ONE DSP48E1 (a 25×18 signed multiplier) instead of the ~10 DSPs a 64×64 multiply decomposes into. The product is sign-extended back to the 64-bit accumulator, so the ADDS and the carried accumulator stay exact 64-bit — the result is byte-identical to the 64-bit fabric (and the VM) whenever the multiply operands fit in mul_bits (which the int8 model guarantees, and the ≡VM locks verify). This is the datapath that makes the spatial array DSP-packable and fast on real silicon.