Function emit_loop_fabric_verilog 

pub fn emit_loop_fabric_verilog(name: &str, lf: &LoopFabric) -> String

Emit the CGRA as a SEQUENTIAL circuit: a combinational body datapath (one wire per SSA value + next-state) plus a controller that clocks the loop-carried state through it once per induction value in lo..=hi. No fetch, no opcode dispatch: the body is WIRED (spatial), the loop is a counter (temporal). done pulses when the loop is finished; result is the returned accumulator.