Skip to main content

emit_fabric_verilog

logicaffeine_compile::codegen_sva::fabric_rtl

Function emit_fabric_verilog 

Source 
pub fn emit_fabric_verilog(
    name: &str,
    n_in: usize,
    ops: &[FabricOp],
    result: usize,
) -> String
Expand description

Emit the residual as a fixed dataflow circuit — one combinational wire per SSA value, no PC / fetch / dispatch. result names the SSA value driving the output. 64-bit, so the circuit’s wrapping arithmetic is bit-identical to the VM’s Int.