pub fn emit_fabric_pipelined_verilog(
name: &str,
n_in: usize,
ops: &[FabricOp],
sched: &PipelineSchedule,
) -> StringExpand description
Emit the scheduled residual as a pipeline: module fabric_{name} with ports clk, in0.., and the registered
result. Every assignment is its own net, so no operator’s signedness leaks into another’s.