Function emit_csa_multiplier_verilog 

pub fn emit_csa_multiplier_verilog(module: &str) -> String

A parameterized Verilog module {module}: an unsigned AW×BW multiplier as a tree of 3:2 compressors over its partial-product rows, registered after CUT tree levels and (with FINAL) once more before a Kogge-Stone final add. One generator for every consumer, so the BigInt limb multiplier and the FPU carry the same tree under their own names.