Constant DECISION_CELLS_BUDGET 

pub const DECISION_CELLS_BUDGET: f64 = 30.0;

The stage budget a decision is cut to on standard cells, in the units of op_delay: three carry chains and their selects. A register is ~20 µm² of flip-flop a bit there, where on a fabric it rides in a LUT’s slice, so a decision takes few stages and reads its ports (Inputs::Ports); each compare takes the sums it reads into its own rows (SumSharing::Fold), resolved by one add synthesis picks (FinalAdd::Native). MEASURED (2026-10-18, K1’s decide so lowered, its ports read, Sky130 HD: yosys 0.33 with OpenLane v1’s DELAY 0 ABC script at a 2 ns target, OpenSTA at the typical corner, no wires): 18 = 5 stages, 44,306 µm² at 4.65 ns; 30 = 3 stages, 34,005 µm² at 3.57 ns; 36 = 2 stages, 30,843 µm² at 5.03 ns; one stage, 32,013 µm² at 7.71 ns. Without the folds, 27 and 30 were 32,750 µm² at 4.10 ns and 31,559 µm² at 4.34 ns.