pub struct Ddr2Grade {Show 20 fields
pub part: &'static str,
pub banks: u32,
pub row_bits: u32,
pub col_bits: u32,
pub dq_bits: u32,
pub cl_floors: &'static [(u64, u64)],
pub tck_max_ps: u64,
pub trcd_ps: u64,
pub trp_ps: u64,
pub tras_ps: u64,
pub tras_max_ps: u64,
pub trc_ps: u64,
pub trrd_ps: u64,
pub tfaw_ps: u64,
pub twr_ps: u64,
pub twtr_ps: u64,
pub trtp_ps: u64,
pub trfc_ps: u64,
pub trefi_ps: u64,
pub tccd_ck: u64,
}Expand description
A DDR2 speed grade: its geometry, the CAS latency each clock period allows, and its datasheet minimums (and the tRAS and tREFI maximums), in picoseconds unless named in clocks.
Fields§
§part: &'static str§banks: u32§row_bits: u32§col_bits: u32§dq_bits: u32§cl_floors: &'static [(u64, u64)](tCK floor, CL) by rising CL: a CAS latency runs at any clock period from its floor up to tck_max_ps.
tck_max_ps: u64§trcd_ps: u64§trp_ps: u64§tras_ps: u64§tras_max_ps: u64§trc_ps: u64§trrd_ps: u64§tfaw_ps: u64§twr_ps: u64§twtr_ps: u64§trtp_ps: u64§trfc_ps: u64§trefi_ps: u64§tccd_ck: u64Implementations§
Source§impl Ddr2Grade
impl Ddr2Grade
Sourcepub const MT47H64M16_25: Ddr2Grade
pub const MT47H64M16_25: Ddr2Grade
Micron MT47H64M16 (1 Gb, x16, 8 banks), speed grade -25: DDR2-800 at CL 6. The Nexys A7-100T carries this part, MT47H64M16HR-25:H. Micron 1Gb DDR2 datasheet, Rev. V 6/10: Table 1 and Table 12’s x16 rows.
Sourcepub const MT47H64M16_25E: Ddr2Grade
pub const MT47H64M16_25E: Ddr2Grade
The same part’s -25E grade: DDR2-800 at CL 5.
Trait Implementations§
impl Copy for Ddr2Grade
impl Eq for Ddr2Grade
impl StructuralPartialEq for Ddr2Grade
Auto Trait Implementations§
impl Freeze for Ddr2Grade
impl RefUnwindSafe for Ddr2Grade
impl Send for Ddr2Grade
impl Sync for Ddr2Grade
impl Unpin for Ddr2Grade
impl UnsafeUnpin for Ddr2Grade
impl UnwindSafe for Ddr2Grade
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