Module ddr2_jedec 

ddr2_jedec — a DDR2 part’s datasheet timing at one clock, and the JESD79-2 command rules a bus trace is held to.

Ddr2Grade is a speed grade as its datasheet prints it: nanosecond minimums and the CAS latency each clock allows. Ddr2Grade::at clocks it: every minimum rounds up to whole clocks (tRRD, tWR, tWTR and tRTP to no fewer than two), every maximum rounds down, and tRPA is tRP + tCK as an eight-bank part’s is. check_bus replays a pin-level command trace against the clocked rules and returns the first violation, or the trace’s facts: what was issued, and every column access with the cycle its data reaches the bus.

Every DDR2 controller the comparative bench drives is judged by this one checker over the commands it put on the bus, so the controllers are compared under the same rules rather than each under its own model. The rules are JESD79-2’s with additive latency 0, write latency CL − 1, and bursts never cut short. A READ or WRITE with A10 high precharges its bank itself: the precharge starts at the later of the clock an explicit PRECHARGE could have come and tRAS after the ACT, and the bank is ready tRP after it. The refresh debt counts from the trace’s cycle 0, when the device is taken as freshly refreshed: by any cycle t it has had at least floor(t / tREFI) − 8 REFRESH commands, eight being the most JESD79-2 lets a controller postpone. A trace that writes a mode register is refused, not judged; that belongs to initialisation, not to the traffic the checker is for.

Structs

BusCmd

One command as the bus carried it: the clock it was sampled on, the command its pins encode, the bank address and the address bus (the row for ACTIVATE, the column and A10 for READ and WRITE, A10 alone for PRECHARGE).

BusFacts

What a legal trace put on the bus. end is the clock after its last command or its last data beat, whichever is later; data_cycles the clocks its bursts held the data bus.

CasEvent

A READ or WRITE, with the row its bank had open and the clock its first data beat occupies the bus.

Ddr2Grade

A DDR2 speed grade: its geometry, the CAS latency each clock period allows, and its datasheet minimums (and the tRAS and tREFI maximums), in picoseconds unless named in clocks.

Ddr2Timing

A grade clocked: every rule in whole clocks. wl is cl − 1, trpa the precharge-all period.

Violation

The first broken rule: the index of the command that broke it (the trace’s length when the trace’s end did), the clock, the rule’s name, and the earlier command or limit it was measured against.

Constants

REFRESH_POSTPONE_MAX

The REFRESH commands JESD79-2 lets a controller postpone: by any clock t it owes at least floor(t / tREFI) − this.

Functions

check_bus

Hold trace to the JESD79-2 command rules of t. NOP and DESELECT entries carry no command and are passed over; every other command must come on a later clock than the one before it.

command_of_pins

The command on the bus for (CS#, RAS#, CAS#, WE#) by the JEDEC truth table, None for the one reserved pattern (RAS# and CAS# high, WE# low) or a level that is not 0 or 1.