pub fn emit_dae_verilog(name: &str, sched: &DaeSchedule, depth: usize) -> StringExpand description
Emit a decoupled schedule as COMBINATIONAL Verilog: the AGU lane (address arithmetic) and the exec lane
(compute + loads) are emitted as two labelled regions, the loads reading a depth-word heap. Bit-identical
to eval_dae (out-of-range loads read 0, matching the model) — proven under iverilog by dae_rtl_lock.
LOAD-ONLY: HeapWrite/HeapAlloc/Func are the sequenced-state follow-on and panic here (the honest
boundary), so the corpus is streaming reads with computed addresses — the canonical DAE case.