Skip to main content

emit_dae_stateful_verilog

Function emit_dae_stateful_verilog 

Source
pub fn emit_dae_stateful_verilog(
    name: &str,
    sched: &DaeSchedule,
    heap_words: usize,
) -> String
Expand description

Emit a decoupled schedule that MUTATES the heap (HeapWrite/HeapAlloc, not just loads) as a SEQUENCED synthesizable datapath: the decoupled layout (AGU cells hoisted first) is run on the proven state-plane micro-sequencer (emit_state_plane_verilog), which commits heap writes in program order over one shared heap + a bump allocator. Module state_{name} (clk/rst/inN/result/done). Bit-identical to eval_dae (≡ the coupled body ≡ the VM); proven under iverilog by dae_rtl_lock. Distinct from the combinational load-only emit_dae_verilog, which realizes the parallel AGU lane for streaming reads.