Module coproc_soc 

coproc_soc — the ULX3S-flashable SoC wrapper around coproc_core.

coproc_core issues BADD/BSUB/BMUL/CMERGE to the synthesized coprocessor blocks and retires to a 256-bit register file, but its rout[255:0] port is 262 pins — impossible on a board. This wrapper makes it real hardware: hold the core in reset, run it to halt, then stream the four RESULT registers (R2..R5) out over a single UART TX line, MSB byte first, each frame preceded by a 0xA5 sync byte. A host (scripts/coproc-host.py) reads the 1 + 128 bytes and checks them against the software model (run_core) — the on-silicon proof of a CPU-issued coprocessor op.

The RTL is FIXED logic (a UART-TX sequencer FSM); only the readout shape depends on the core (four 256-bit result registers). The testbench’s expected registers are DERIVED from run_core, so a change to the coprocessor semantics regenerates the golden in lockstep — no hand-typed hex. The wrapper .v, its testbench, and the board constraints are drift-locked; the iverilog PASS + the routed coproc_soc.bit are recorded in benchmarks/silicon/reports.json.

Constants

RESULT_REGS

The result registers streamed out, in order: R2=BADD, R3=BSUB, R4=BMUL, R5=CMERGE.

Functions

emit_coproc_soc_testbench

Emit the self-checking testbench. The expected result registers are DERIVED from run_core (not hand-typed): the tb decodes the UART TX stream, reconstructs the sync byte + 128 payload bytes, and checks each MSB-first byte against the model’s retired R2..R5. PASS iff every byte matches — the software≡RTL proof over the serial framing.

emit_coproc_soc_verilog

Emit the flashable SoC wrapper: coproc_core + a 7-state UART-TX readout FSM. External pins (clk, rst, uart_tx, led[7:0]) fit the ULX3S; CLKS_PER_BIT = clk_hz / baud (217 for 25 MHz / 115200). The RTL is operand-independent — the core carries the operands internally.

emit_ulx3s_coproc_lpf

Emit the ULX3S (LFE5U-85F caBGA381) board constraints: 25 MHz clock (G2), reset = FIRE1 (R1), UART TX → FTDI RXD (L4), 8 LEDs. Sites from the board’s ulx3s_v20.lpf.

expected_stream

The 129-byte serial frame the SoC streams: a 0xA5 sync byte, then R2..R5 (256-bit each), most-significant byte first. This is exactly what scripts/coproc-host.py reconstructs and what tb_coproc_soc.v samples off the wire — the single definition of the readout order.