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Module computedram_rtl

Module computedram_rtl 

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computedram_rtl — Phase 4: the in-DRAM compute path proven end-to-end in simulation.

A behavioral device that IMPLEMENTS the ComputeDRAM effect: on the ACT→PRE→ACT cadence (an ACT, an interrupted precharge, then a second ACT with no RD/WR between — the signature emit_computedram_stream produces), it performs RowClone (dst := src). Driven by the proven dram_executor (which issues the delta-encoded raw sub-JEDEC command stream), it lets a ComputeDramOp execute as real commands and yields a result checked against the RowStore/VM oracle — “compute over RAM,” proven in sim.

This models the CHIP computing; whether the physical Micron DDR2 exhibits the effect is the Phase-3 characterization (which may differ). The harness plays the role of the fabric orchestrating the op: it places the operand row, triggers the stream, and reads the result back.

Functions§

emit_computedram_harness_testbench
Emit tb_computedram — the harness (the fabric’s role): preload src with pattern, replay the delta-encoded ComputeDRAM stream (cdram_plan.hex) through dram_executor into the device, then read dst and assert it equals pattern (the RowClone oracle). nwords = stream length.
emit_computedram_model_verilog
Emit computedram_model — the behavioral ComputeDRAM device. On the ACT→PRE→ACT compute cadence it performs RowClone (2 activations: dst := src); on ACT→PRE→ACT→PRE→ACT (3 activations) it performs the sense-amp triple-row MAJORITY over the ORIGINAL operand values, writing it to all three rows — so bitwise AND = MAJ(a,b,0) and OR = MAJ(a,b,1). Snapshots the originals so the tentative 2-row clone can be corrected by a 3rd activation. A RD/WR closes the cadence. Preload/read ports for the harness (which plays the fabric’s orchestration role).
emit_computedram_reduce_testbench
Emit tb_computedram_reduce — proves in-DRAM bitwise AND and OR via triple-row activation. Preloads operands (a=aval, b=bval, zero=0 for AND with a 0 control; a2=aval, b2=bval, ones=~0 for OR with a 1 control), replays the concatenated Maj streams from cdram_reduce.hex, and asserts the majority result: mem[a] == aval & bval (AND = MAJ(a,b,0)) and mem[a2] == aval | bval (OR = MAJ(a,b,1)).