Module chan_rtl 

chan_rtl — the deterministic channel in silicon: a bounded FIFO.

The language’s Pipe is a FIFO, bounded, move-semantics channel (logicaffeine_runtime::channel::Chan): values leave in the order they entered, a full buffer refuses a sender (has_room = len < capacity), an empty buffer refuses a receiver. This module emits that exact discipline as a synthesizable sync FIFO and proves, under iverilog, that replaying an arbitrary send/recv trace produces the same pop sequence as the software channel’s bounded VecDeque — the channel’s determinism, in hardware.

It is one channel’s buffer. The multi-node routing/rendezvous (who is connected to whom, select, blocking hand-off across cores) stays the scheduler/message-passing layer — a projection, not this block.

Functions

emit_chan_fifo_testbench

A self-checking testbench: replay an N-step (push, pop, din) trace and compare the DUT’s pop sequence against the software channel oracle from chan_{ctrl,din,pops}.hex.

emit_chan_fifo_verilog

Emit the bounded sync FIFO: combinational front-read (dout), combinational full/empty/ handshake, registered pointers + count. pushed = push & !full, popped = pop & !empty.