Module caravel_rtl 

caravel_rtl — the Infinichip command player wrapped as an efabless Caravel user macro, the step that makes it literally shuttle-integratable.

A real Caravel submission keeps efabless’s golden user_project_wrapper.v VERBATIM and only swaps the user macro instantiated inside it. So the artifact WE own is that macro: dram_executor_wb — the countdown command player (codegen_sva::dram, decode + issue-timing certified by our own SAT) behind a standard Wishbone slave, with the issued command exposed on the logic-analyzer bus for observation. The management SoC writes the 64-bit compile-time plan word over Wishbone (two 32-bit stores), strobes launch, and the certified FSM issues.

Register map (Wishbone byte offsets, caravel user base 0x3000_0000):

0x00  W  cmd_word[31:0]           0x0C  R  {issued, bank, op} status
0x04  W  cmd_word[63:32]          0x10  R  row of the last issued command
0x08  W  bit0 = launch (cmd_valid)

la_data_out[63:0] = {issued, 0, bank, op, row} — live observation on the logic analyzer.

Wishbone conventions match user_proj_example (valid = cyc & stb, single-cycle ack).

Functions

emit_dram_executor_wb_testbench

A self-checking Wishbone testbench: the “management SoC” writes a delta-0 plan word (op=1, bank=3, row=7) over Wishbone, strobes launch, and asserts the certified FSM issues that exact command — observed on la_data_out. Prints PASS/FAIL; no external vectors.

emit_dram_executor_wb_verilog

Emit the SELF-CONTAINED user macro: the certified dram_executor + the dram_executor_wb Wishbone front end. This is the design hardened + golden-DRC’d + dropped into Caravel’s golden user_project_wrapper for a shuttle submission.

emit_dram_user_project_verilog

Emit the SELF-CONTAINED full-interface user macro: dram_executor + dram_executor_wb core + dram_user_project. This is the macro hardened (with power pins + tap insertion) and placed as mprj inside the golden user_project_wrapper for a shuttle submission.

emit_user_project_wrapper_around

Emit a user_project_wrapper — the efabless golden Caravel wrapper interface, verbatim ports, instantiating the full-interface user macro macro_module as mprj and connecting EVERY wrapper pin 1:1 (the passthrough that makes the placed-and-routed wrapper LVS-clean). carries names what the macro holds, for the header.

emit_user_project_wrapper_verilog

Emit our user_project_wrapper for the DRAM command player: emit_user_project_wrapper_around dram_user_project.