pub fn unpipelined(graph: &TimingGraph) -> Result<(TimingGraph, i64), PipeError>Expand description
The logic of a pipeline with its registers taken out, and the latency they made: a graph pipeline cuts afresh
at any period. A pipeline’s registers are plain flip-flops, one registered edge into each, and every path from its
inputs to a node holds as many of them, so every output is the same number of clocks late; taken out, each is a wire
from its data, or its data’s constant when the source hands it one. A register with more in than its data (an
enable, a reset, a memory’s port) is refused by name, and so is a node whose paths hold different numbers of
registers; a register in a loop leaves logic looping through none.