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emit_seeded_arbiter_verilog

logicaffeine_compile::codegen_sva::arbiter_rtl

Function emit_seeded_arbiter_verilog 

Source 
pub fn emit_seeded_arbiter_verilog() -> String
Expand description

Emit the clocked SplitMix64 draw core: on each step, advance the state and present the mixed 64-bit draw on draw with draw_valid. Combinational mixing, registered state — one draw per requested step, deterministic from the loaded seed.