Module arbiter_rtl 

arbiter_rtl — the deterministic NoC arbiter’s entropy core in silicon.

The handout claims a “deterministic (seeded, reproducible) interconnect” — the same seeded scheduler our concurrency runtime already ships (logicaffeine_system::concurrency::seeded_pick, a SplitMix64 draw). This module emits that draw source as synthesizable RTL and proves, under iverilog, that the hardware draw sequence is byte-identical to the software scheduler’s for the same seed — so a message-passing schedule replays identically whether it ran on the CPU runtime or the chip’s NoC.

The below(n) reduction (draw % n, with the runtime’s “n<=1 ⇒ 0 without drawing” rule) is a thin wrapper over this core; the core IS the reproducible entropy, so it is what the differential pins.

Constants

ARBITER_TEST_SEED

The fixed seed the arbiter differential uses (a stand-in for LOGOS_SEED).

SM64_GAMMA

The SplitMix64 golden constants — IDENTICAL to logicaffeine_system::concurrency::SplitMix64.

SM64_MIX1

SM64_MIX2

Functions

emit_seeded_arbiter_testbench

A self-checking testbench: load a seed, step N times, and compare each hardware draw against the software oracle sequence from arbiter_seq.hex. Prints PASS/FAIL.

emit_seeded_arbiter_verilog

Emit the clocked SplitMix64 draw core: on each step, advance the state and present the mixed 64-bit draw on draw with draw_valid. Combinational mixing, registered state — one draw per requested step, deterministic from the loaded seed.

sm64_next

The software SplitMix64 draw — mirrors the runtime, the oracle the RTL is checked against.