pub fn precise_operands(operand_text: &str) -> (Vec<u8>, Vec<u8>)Expand description
PRECISE operand decode from the nvdisasm TEXT of one instruction (everything after the mnemonic, before the
;). nvdisasm already prints the exact registers, so we parse them rather than reverse-engineer the binary
operand fields. Returns (writes, reads) as register numbers (RZ/255 dropped). Rules, verified against real
SASS: operand 0 is the WRITE destination UNLESS it is a memory ref [...] (a store — then it’s a read
address and nothing is written); every other operand is a READ; registers inside [...] are address reads;
a .64/.128 width on an address adds the consecutive address registers; accumulate ops (IMMA/FFMA)
naturally read their destination because it reappears as a later operand. Groups {R8,R9,...} expand.