Module codegen_riscv 

LOGOS → RISC-V AOT codegen tier. Lowers the register bytecode CompiledProgram — the SAME IR the WASM backend and the Silicon ISA emitter consume — to RV64GC assembly text (SysV lp64d ABI, glibc), which a RISC-V GCC assembles+links and qemu-user runs, byte-for-byte identical to the VM.

Structurally this mirrors crate::vm::isa::emit_isa (a CompiledProgram → String text emitter), and its totality discipline mirrors the WASM tier: every op the current phase does not lower returns RiscVLowerError::Unsupported — a SOUND refusal, never a miscompile — and the riscv_coverage_lock ratchet forces each such op onto a shrink-only KNOWN_GAPS list so nothing is silently wrong.

Register model (v1): each VM virtual register is one 8-byte STACK SLOT at (8*reg)(sp); every op loads operands into scratch (t0..t2), computes, and stores the result back. No values live in registers across instructions, so lowering is a local, context-free transliteration and calls are trivially correct (no caller-saved value is live across a call). A real register allocator is a later optimization.

Structs

Runtime

What a RISC-V program links beside its assembly: the C of its runtime shim, and what its link line names after the assembly and the shim.

Enums

RiscVLowerError

An op / type / shape outside the current phase’s supported fragment. The &str names what is not yet lowered (an op name, or a reason like "Show of non-scalar value"). A refusal — the backend declines to emit rather than emit wrong code (mirrors crate::vm::wasm::WasmLowerError).

Constants

RISCV_RUNTIME_C

logos_show_f64 renders an f64 EXACTLY like the VM’s Show (Rust’s {} Display: shortest decimal that round-trips, NEVER scientific notation, bare integral floats, NaN/inf/-inf/-0). It finds the shortest significant-digit count whose %e form round-trips via strtod, then reformats that to fixed decimal notation so any magnitude prints without an exponent — matching Rust for every finite value. Called with the double in fa0 (a named param, so no variadic-FP marshalling needed).

Functions

codegen_program_riscv

Emit program as RV64GC assembly text. Returns RiscVLowerError::Unsupported if the program uses any op/shape outside the currently-lowered fragment.

links_value_runtime

Whether the RV64GC assembly asm links the exact extension’s value runtime: it defines VALUE_RUNTIME_SYMBOL.

mutates_own_collection

Whether this tier lowers op as a value-semantics mutation of a register’s own collection or Text, or of a value in its own record’s field: through an _own runtime helper that copies first only what the register’s owned flag (and, for a field, its field flag) says may be held elsewhere, so the change never reaches an alias and a loop of them runs in place.

runtime

The runtime the assembly asm links. A program the exact extension never reaches links RISCV_RUNTIME_C and the math library. One it reaches links the shim with the extension’s adapter after it (the extension’s C core over the shim’s collector, then the entry points the assembly calls), and logicaffeine-data’s value runtime built for RV64GC Linux with the system libraries it calls, statically.