Module codegen_dram 

codegen_dram — the DRAM compute-in-memory target (ComputeDRAM bulk bitwise + RowClone).

DRAM-via-ComputeDRAM is a CO-PROCESSOR target, like crate::codegen_ana: it realizes a restricted op subset (the charge-sharing sense amps do bulk bitwise AND/OR and RowClone), and everything else runs on the host/fabric control side. So it uses the same FOUR-way split as the analog tier:

• OnPlane — bitwise/copy the DRAM sense amps compute in place, each with a witnessed ComputeDramOp realization proven ≡VM by the RowStore oracle and the unified_placement equivalence locks;
• Boundary — data staging: operand rows written into the DRAM, result rows read back out;
• ControlPlane — digital-exact ops the host runs VM-identically (arithmetic, comparisons, control flow — the DRAM has no ALU and no sequencer), refusing nothing;
• OffPlane(reason) — refuses the whole DRAM offload (concurrency / networking — there is no scheduler or host-IO story inside a memory device).

fragment is an EXHAUSTIVE match on Op (no _ arm): a new VM instruction fails to compile this crate until it is deliberately classified — the anti-drift pit of success. dram_prim ties every OnPlane op to the exact ComputeDRAM primitive that realizes it, and the op-coverage ratchet (tests/dram_op_coverage_lock.rs) proves that primitive is DRAM-capable and ≡VM. You cannot mark an op OnPlane without a proven in-DRAM realization.

Beyond the single-op layer, dataflow is the SPATIAL-DATAFLOW layer: the hardware basis {Copy, And, Or} (ComputeDRAM) + Not (Ambit) is functionally complete, so chaining primitives through intermediate rows realizes any boolean function and, bit-serially, integer arithmetic — the memory computes a dataflow graph in place.

Modules

dataflow

DRAM dataflow composition — the spatial-dataflow layer of the compute-in-memory target.

kernels

DRAM application kernels — the workloads in-memory compute is lightning-fast at: bitwise + COUNT over massive data, at zero data movement. Popcount is the linchpin — the reduction that turns the bitwise/XNOR machinery into counts, distances, and dot products:

set_algebra

Set algebra on the DRAM plane — the COMPLETE finite set algebra over BITSET-encoded sets, lowered to DRAM dataflow kernels. A set over a bounded universe is a bit vector (a row): membership of element i is bit i. Over that encoding the set algebra IS the bitwise algebra —

Enums

DramFragment

Where an op lives in the DRAM-co-processor model.

DramLowerError

Why the DRAM tier declines a program — a SOUND refusal, never wrong memory.

DramTier

The in-DRAM hardware tier an OnPlane op needs — the HONEST hardware assumption. Copy/AND/OR run on UNMODIFIED off-the-shelf DRAM (ComputeDRAM, Gao et al. MICRO 2019); XOR needs the AMBIT tier (dual-contact cells, a minor DRAM modification; Seshadri et al. MICRO 2017). None iff not OnPlane.

Functions

dram_prim

For an OnPlane op, the ComputeDRAM primitive that realizes it (proven ≡VM in unified_placement). None for every non-OnPlane op — the op-coverage ratchet asserts this biconditional (OnPlane ⟺ dram_prim is Some).

dram_refusal

The fail-closed refusal gate every DRAM offload runs FIRST. None means the program clears the gate (a bulk-bitwise/copy region exists, inside the memory-device model).

dram_tier

fragment

★ THE SINGLE SOURCE OF TRUTH ★ for how the DRAM tier classifies every VM op. EXHAUSTIVE on Op (no _ arm) — a new instruction cannot escape classification.

has_bitwise_region

Whether the program carries any OnPlane bulk-bitwise/copy work — the DRAM-region existence probe.

unsupported_reason

Returns Some(reason) if program uses an op with no home in a memory device — concurrency (a DRAM has no thread scheduler) or networking (host-only IO). Shares the offload classifier with the other single-device tiers so they cannot drift.