Module reduction 

The streamed reduction — the flagship MAC lane.

A float-accumulator loop over a sequence (Repeat for each x in xs: Set acc to acc + …) becomes ONE analog tick datapath run once per element under the control plane’s frame schedule: the element is validated (the Assume contract), DAC-driven, the plane settles, and the sample-and-hold commits the new accumulator — which LIVES IN ANALOG between frames, never re-quantized. Only the final accumulator crosses the ADC. That asymmetry (per-element DAC cost, one ADC, zero mid-stream conversions) is the analog win this lane exists to state.

Semantics are sampled-data ZOH: each frame’s update is exact arithmetic over the held element, so the ideal tier reproduces the VM’s loop trajectory bit-for-bit, and the physical tier (converters + quantized weights) stays inside a budget ITERATED over the declared maximum frame count — which is why a Assume length of xs is between A and B. contract is REQUIRED: a budget over an unbounded stream would be a guess, and this lane does not guess.

Extraction reuses the digital fabric’s certified counted-loop front-end (loop_fabric_from_source, read-only) on the contract-free twin, exactly like the DAG lane.

Structs

AnalogReduction

A lowered streamed reduction. Tick-input convention: In(0) = the streamed element, In(1) = the held accumulator; out = the next accumulator value.

Functions

analog_int_reduction_from_source

Lower a Seq of Int accumulator loop to a GRID-PRESERVING streamed reduction — the integer MAC. The exactness claim is made downstream by super::exactness_gate over the iterated budget.

analog_reduction_from_source

Lower fn_name (a single-Seq of Float-parameter accumulator loop) to a streamed analog reduction realizable on target.

eval_analog_sampled

Ideal sampled evaluation: the VM’s loop trajectory, tick by tick (bit-exact — same f64 ops in the same order).

eval_analog_sampled_quantized

The physical sampled tier: each element DAC-quantized on entry, the accumulator CONTINUOUS across frames (it lives in the S&H), one ADC quantization at the end — over the weight-quantized tick.

reduction_error_budget

The reduction budget: the shared ε engine ITERATED over the declared maximum frame count — the element’s DAC half-LSB enters every frame, the weight-snap deviation injects every frame, the accumulator’s lanes carry, and one ADC half-LSB lands at the end.

reduction_scale_pass

Schedule + certify the reduction: quantize the tick’s weights, ITERATE the interval propagation over the declared maximum frame count (hulling per net), choose the block scale over the whole trajectory, and emit the certificate the independent checker replays with the same iteration.