Expand description
Factory calibration — manufacturing ADJUSTABLE circuits, not impossibly perfect ones.
Production test measures each die through the loopback paths (DAC → tile → ADC), computes
per-leg gain trims and per-tile offset trims on the trim grid, and burns them beside the
configuration. The effective die is compiler programming + per-die calibration; what the
budget then carries for gain and offset is the RESIDUAL — half a trim step, a deterministic
bound, instead of the full k·σ manufacturing envelope. Noise cannot be trimmed and keeps its
envelope. This is the lever that turns per-die physics into a product-grade ε.
Structs§
- Calibration
Table - Per-die trim values, each ON the trim grid.
- Trim
Spec - The trim DAC resolution — a design parameter of the tile (finer than the weight grid, since trims correct errors, not values).
Functions§
- apply_
calibration - The calibrated die: residual gain/offset errors (≤ half a trim step by construction), the noise realization untouched (noise is dynamic — no trim reaches it).
- calibrate
- Factory calibration of one measured die: the quantized negation of every measured error.
- error_
budget_ calibrated - The CALIBRATED physical budget: gain and offset carry the residual half-step bound instead of the k·σ manufacturing envelope; noise keeps its envelope; the converter/quantization terms are unchanged.
- v1_trim
- The V1 tile’s trim resolution: gain trim = a quarter unit element; offset trim = 0.5 mV steps (a 6-bit trim over ±16 mV). Design parameters of OUR tile, not silicon claims.