Module accel 

The accelerator backends’ shared framework: the analog plane, the Plasticine PCU mesh and the SambaNova RDU all run a program the same way, as a host program with device regions.

• region: the functions a device runs, lowered from the host’s own optimized program to control-flow graphs over checked cells, each held to the VM.
• lane, multiword, int64, softfloat, cells: every cell as a routine over the lane words a device actually has, with no binary64 or 64-bit unit assumed.
• c_model: the executable device model, generated from the regions and their routines, that a host binary links on a machine with no accelerator.

Modules

c_model

The executable device model as C: what the host binary links and calls when it runs on a machine that has no accelerator.

cells

Each region cell as a lane routine: the fabric’s checked 64-bit semantics (AluOp/FuncUnit/CmpKind::eval_checked) realized at a device’s lane shape by the multi-word core and the softfloat.

int64

The VM’s 64-bit integer operations on narrow lanes: each is the checked semantics of fabric_rtl::{AluOp, FuncUnit, CmpKind}::eval_checked, built from the multi-word core. A result that leaves i64, a zero divisor or an exponent the VM refuses is reported in the fault word as the divergence’s code, never as a wrapped value.

lane

The lane machine: what a device’s integer datapath can actually do, at the width it actually has.

multiword

The multi-word integer core: every wider-than-a-word integer operation, built once from lane operations and parameterized by the lane shape.

region

Regions: the functions an accelerator runs, as control-flow graphs over checked cells.

softfloat

IEEE-754 binary64 on integer lanes: the VM’s Float arithmetic, exact to the bit, for devices whose silicon has no binary64 unit.